Conventional stacked capacitor DRAW arrays utilize either a buried bit line or a non-buried bit line construction. With buried bit line constructions, bit lines are provided in close proximity to the bit line contacts of the memory cell FETs, with the cell capacitors being formed horizontally over the top of both of the word lines and bit lines. With non-buried bit line constructions, deep vertical contacts are made through a thick insulating layer to the cell FETs, with the capacitor constructions being provided over the word lines and beneath the bit lines. Such non-buried bit line constructions can also be referred to as capacitor-under-bit line or bit line-over-capacitor constructions.
With respect to bit line-over-capacitor constructions, the storage node polysilicon of the capacitor is not as large as it could otherwise be as one must provide room for the vertical contacts down to the cell FETs. Additionally, there are at least three potential areas of misalignment in bit line-over-capacitor constructions. A first is with respect to patterning and etch of the storage node poly. A second is with respect to etch of the cell poly. A third is with respect to bit line contact formation. Because of process design rules implemented to ensure a high proportion of operable chips, it is necessary to reduce the size of the storage node poly and increase the area for bit line contacts to allow for inevitable photomask misalignment. However such consumes space on the wafer, and correspondingly adversely impacts cell density.
Such are not predominate factors with buried bit line fabrication. However with buried bit lines, there are other areas of increased process complexity resulting from added photomask and etching steps. Also, buried bit line constructions require additional deposition steps beyond bit line-over-capacitor constructions.
It would be desirable to minimize or overcome these and other aspects associated with prior art bit line-over-capacitor arrays.